Intel Corp (NASDAQ:INTC) is leaning towards advanced chip packaging tech in its battle for supremacy in the chip-making industry. During the 2020 Intel Architecture Day, we were reminded that various transistor designs are necessary when building heterogeneous systems.
Intel lays a plan for its innovative packaging approaches
Raja Koduri, the company’s chief architect, said no single transistor is optimal in all design points. Koduri said that the transistor required for a performance desk CPU to hit high frequencies is different from the chip required for high-performance integrated GPUs. Collecting processing cores, graphic resources, fixed-function accelerators, and I/O and drawing them into a 10nm monolithic die presents challenges when manufacturing. However, the option of breaking them and linking pieces has challenges of its own, but innovations in packaging circumvent the challenges by improving the interface between the dense circuits and boards they populate.
In 2018, Intel indicated that it was planning to have small devices working together without compromising speed. Koduri said that they had indicated they will connect tech to connect chiplets and chips in a package matching performance, power efficiency, and the cost of monolithic SoC. Equally, the company had indicated that they needed high density to interconnect roadmap enabling high bandwidth at low power.
Intel looking to take the lead in chip packaging
Currently, competition in the industry is all about who will produce the best process tech, and innovative packaging approaches will be the differentiator in the battle for supremacy. Intel’s packaging playbook comprises an embedded multi-die interconnect bridge (EMIB) that facilitates die-to-die connections through tiny silicon bridges incorporated in the package substrate.
The EMIB will mitigate the 2.5D packaging limitations by doing away with the interposer in favor of silicon bridges. Ramune Nagissetty, the company’s process, and product integration director said that the current generation EMIB has a 55-micron Micro-bump pitch, and they are on course to get 36 microns. The packaging also includes an advanced interface bus, an open-source interconnecting standard for creating high-bandwidth connections.